Phase-locked loop (PLL) circuits are widely implemented in many applications for "locking" an oscillator in phase with a reference signal. These circuits are frequently employed, for example, in digital communication systems for generating a local clock signal that is phase aligned with an incoming reference signal. The phase aligned local clock signal facilitates the receipt and processing of synchronous data sent by a transmitter in the communication system. PLL circuits also have use in numerous other applications (e.g., FM receivers, portable cellular phones, spread spectrum receivers, etc.).
FIG. 1 illustrates a conventional PLL circuit implemented in an integrated circuit for frequency synthesis. Frequency synthesis involves producing frequencies that are multiples of a reference frequency. The reference source 101, which is typically a crystal oscillator, outputs a reference signal to a reference divider 103, which then supplies a divided reference signal to a phase comparator 105. A voltage controlled oscillator (VCO) 113 also provides a VCO signal to a VCO divider 111, which outputs a divided VCO signal. The phase comparator 105 detects the phase difference between the divided reference signal and the divided VCO signal and outputs a corresponding phase error signal. The phase error signal is outputted to a charge pump 107, which supplies a current that is proportional to the phase error. The current is then filtered via a low-pass filter (LPF) 109 and applied to the control input of the VCO 113 to produce an output signal that tracks the phase of the divided reference signal. The process continues until a zero phase error is attained, whereby the two frequencies are properly aligned.
Channel switching time, which is a measure of performance of a PLL circuit, represents the ability of the PLL circuit to switch from a given channel (VCO frequency) to another channel. To achieve a shorter switching time, channel bandwidth can be increased within the general frequency spacing, but results in significant noise contribution from the charge pumps. In the past, switching time was not a primary concern, allowing use of narrow bandwidths, which permits the PLL circuit to be tolerant of "noisy" charge pumps. However, switching time is now of greater concern due to requirements for faster switching. Because channel bandwidth is increased, noise within the charge pump is more pronounced, having greater detrimental impact on the PLL circuit performance.
Charge pumps, in general, introduce low frequency phase noise into the PLL circuit. An exemplary charge pump 107 is implemented as a differential charge pump, as shown in FIG. 1, in which two current sources 107a, 107b are required for linear operation. A typical differential charge pump is disclosed in European Patent No. EP 0 718 978 A1 to Bruccoleri et al. According to FIG. 1, one current source 107a ("Ppump") charges a storage capacitor (not shown); while the other current 107b ("Npump") discharges it. That is, the Ppump supplies current to the filter. During simultaneous operations, these current sources 107a, 107b produce substantial noise within the PLL circuit. Additionally, offset due to dynamic mismatch of the Npump and Ppump as well as direct current (DC) mismatch adversely affects the circuit by introducing more noise. DC mismatch arises because the charge pump is either OFF or switching most of the time; thus, the charge pump is ON only for a short duration. Charge pump noise appears in the VCO spectrum, potentially causing inaccurate locking or even non-locking by the VCO.
In an attempt to address these problems, a number of techniques have been developed to reduce charge pump noise; e.g., reduction of dynamic and static mismatch between the Ppump and Npump, reduction of the differential mode noise, suppression of the common mode noise, and augmentation of device switching speed. However, these techniques disadvantageously rely on the low frequency noise response of the output devices. Because noise is inherent in the components themselves, noise cancellation may not be possible. Further, some of the prior art methods are difficult to implement and are not applicable to various types of PLL circuitry (e.g., fractional-N frequency synthesizers).